1 tn1504 features low threshold (2.0v max.) high input impedance low input capacitance (50pf typ.) fast switching speeds low on-resistance free from secondary breakdown low input and output leakage complementary n- and p-channel devices applications logic level interfaces C ideal for ttl and cmos solid state relays battery operated systems photo voltaic drives analog switches general purpose line drivers telecom switches ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? general description this low threshold enhancement-mode (normally-off) transis- tor utilizes a vertical dmos structure and supertexs well- proven silicon-gate manufacturing process. this combination produces a device with the power handling capabilities of bipolar transistors, and with the high input impedance and positive temperature coef? cient inherent in mos devices. characteristic of all mos structures, this device is free from thermal runaway and thermally -induced secondary breakdown. supertexs vertical dmos fets are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input im- pedance, low input capacitance, and fast switching speeds are desired. absolute maximum ratings parameter value drain-to-source voltage bv dss drain-to-gate voltage bv dgs gate-to-source voltage 20v operating and storage temperature -55 o c to +150 o c absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. ordering information device order number bv dss / bv dgs (v) r ds(on) (max) () v gs(th) (max) (v) i d(on) (min) (a) die* tn1504 TN1504NW 40 3.0 2.0 2.0 * die in wafer form. n-channel enhancement-mode vertical dmos fets
2 tn1504 sym parameter min typ max units conditions electrical characteristics (t a = 25 o c unless otherwise speci? ed) switching waveforms and test circuit bv dss drain-to-source breakdown voltage 40 - - v v gs = 0v, i d = 1.0ma v gs(th) gate threshold voltage 0.6 - 2.0 v v gs = v ds , i d = 0.5ma ?v gs(th) change in v gs(th) with temperature - -3.8 -5.0 mv/ o c v gs = v ds , i d = 1.0ma i gss gate body leakage - 0.1 100 na v gs = 20v, v ds = 0v i dss zero gate voltage drain current -- 10 a v gs =0v, v ds = max rating v ds = 0.8 max rating v gs = 0v, t a = 125 o c 500 i d(on) on-state drain current -1.4- a v gs = 5v, v ds = 25v -3.4- v gs = 10v, v ds = 25v r ds(on) static drain-to-source on-state resistance - 2.0 4.5 v gs = 4.5v, i d = 250ma -1.63.0 v gs = 10v, i d = 500ma ?r ds(on) change in r ds(on) with temperature - 0.6 1.1 %/ o c v gs = 10v, i d = 0.5a g fs forward transconductance 225 400 - mmho v ds = 25v, i d = 500ma c iss input capacitance -5060 pf v gs = 0v, v ds = 25v, f = 1.0mhz c oss common source output capacitance -2535 c rss reverse transfer capacitance - 4.0 8.05 t d(on) turn-on delay time - 2.0 5.0 ns v dd = 25v, i d = 1.0a r gen = 25 t r rise time - 3.0 5.0 t d(off) turn-off delay time - 6.0 7.0 t f fall time - 3.0 6.0 v sd diode forward voltage drop -1.01.5 v v gs = 0v, i sd = 0.5a t rr reverse recovery time - 400 - ns v gs = 0v, i sd = 0.5a notes: 1. all d.c. parameters 100% tested at 25c unless otherwise stated. (pulse test: 300s pulse, 2% duty cycle.) 2. all a.c. parameters sample tested. 90% 10% 90% 90% 10% 10% pulse generator v dd r l output d.u.t. t (on) t d(on) t (off) t d(off) t f t r input input output 10v v dd r gen 0v 0v doc.# dsfp-tn1504 a102907
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